1. Field of the Invention
The present invention relates to the field of semiconductor manufacturing and more specifically to a method of forming a highly doped polysilicon thin film.
2. Discussion of Related Art
Conventional complementary metal oxide semiconductor (CMOS) integrated circuits are fabricated with doped polysilicon gate electrodes. An example of a conventional method of fabricating a CMOS integrated circuit is illustrated in FIG. 1A-1C. First, as shown in FIG. 1A, a gate dielectric layer 106 is formed over a p type region 102 and an n type region 104 of a silicon monocrystalline substrate 100. A polycrystalline silicon film 108 is then blanket deposited over the gate dielectric layer 106 as shown in FIG. 1A. The polycrystalline silicon film is then patterned with conventional techniques into gate electrodes 110 and 112 as shown in FIG. 1B.
Next, as shown in FIG. 1C, n type dopants 114 are implanted into the p type region to form n type source/drain regions 116 and p type dopants 118 are implanted into the n type region 104 to form n type source/drain regions 120. The source/drain implants are also used to dope the undoped polysilicon film of gate electrodes 110 and 112 to n type and p type conductivity, respectively. A high temperature activation anneal, such as a rapid thermal anneal is then used to activate the dopants.
“Poly depletion” effects are becoming a limiting factor in one's ability to further scale device dimensions so that higher density and more complex integrated circuit can be fabricated. “Poly depletion” is caused by the fact that the ion implantation and activation anneal are unable to obtain a sufficiently high dopant concentration at the gate electrode/gate oxide interface resulting in a larger effective thickness of the gate oxide which degrades device performance. In order to increase the active dopant concentration at the gate electrode/gate dielectric interface, it has been proposed to increase the implant energy/dose and/or to utilize higher temperature activation annealing. Increasing anneal temperatures can lead to excessive diffusion of dopants in the junction regions degrading device performance. Additionally, increasing the implant energy/dose can lead to the penetration of dopants through the gate oxide. Additionally, it has been suggested to use ultra fast annealing techniques, such as laser annealing, to increase the dopant activation and concentration at the interface. Unfortunately, laser annealing processes can be difficult to control and laser annealing patterned polysilicon features can cause melting of the polysilicon feature resulting in defects, such as poly “feet”.